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INDEX PRELIMINARY
MX98704
100BASE-TX PHYSICAL DATA TRANSCEIVER
1.0 FEATURES
* * * * * * * * * * * Full-Duplex Operation Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data Converts Transmit NRZ Data to NRZI Data Loopback and Transmitter-Off Modes Recovers 125-MHz Clock from Incoming serial NRZI Data Stream Reclocks Incoming Serial NRZI Data Stream Using Recovered Clock Converts Received Serial Bit Stream to 5-Bit Paralled Form Converts NRZI data to NRZ Generates 25-MHz Receive Clock Package type -52 PLCC -52 PQFP
2.0 GENERAL DESCRIPTION
The 100Base-Tx Physical Data Transceiver (PDTR) includes the Physical Data Transmitter (PDT) and the Physical Data Receiver (PDR). The PDT converts encoded symbols into a serial NRZI data stream. The on-chip PLL generates a bit rate clock from the TCLKIN or crystal reference. The PDR uses a built-in clock recovery PLL to extract clock information from the received data stream. The recovered clock is used for serial-to-parallel data conversion.
2.1
FUNCTIONAL BLOCK DIAGRAM
TDAT4-0
Input Register
Shifter
NRZ/ NRZI
Output Control
TDH, TDL
SYMCLK
TXEN
XTAL1, XTAL2 TCLKIN
25 Mhz Crystal Oscillator
Clock Multiplier (PLL)
NRZ/ NRZI RDAT4-0 Output Register Shifter Media Interface RDH, RDL
SDO RSCLK Divided by 5 Clock & Data Recovery (PLL) Clock Generator Control Logic MUX Normal Mode Test & Loopback Signal Detect SDI
TEST LPBKB
Data Transceiver Functions Block Diagram
P/N : PM0351 REV. 1.4, SEP. 15, 1997
1
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MX98704
2.1.1 100 BASE-TX HUB APPLICATION
TD(0:4) MX98741 (Repeator Controller) RD(0:4) SD MX98704 TD(+, -) SD+ RD(+, -) MX98702 xformer
8 ports
100 BASE-TX HUB SYSTEM DIAGRAM
2.1.2
10/100-TX NIC APPLICATION
TD(0:4) MX98713 (MAC) 10BASE-T TRANSCEIVER SD RD(0:4) MX98704
TD(+, -) SD+ RD(+, -) MX98702
TD(+, -) RX(+, -) xformer
10/100-TX NIC Application
2.2
SYSTEM APPLICATION
The MX98704 can be used in 100 BASE-TX HUB application, and 10/100-TX NIC application.
2
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MX98704
3.0 PIN ASSIGMENT
3.1 PIN ASSIGNMENT-52 LEAD PLASTIC LEADED CHIP CARRIER
GND NC VDD RCP GND VDD GND VDD GND VDD RT LP RSCLK
7 OP1 NC NC VDD SDI NC RDL RDH VDD NC OP2 TDH TDL 8
1
47 46
MX98704
20 21
34 33
SDO RDA0 RDA1 RDA2 RDA3 RDA4 TS TDA0 TDA1 TDA2 TDA3 TDA4 TCKIN
3.2
PIN ASSIGNMENT-52 PQFP
GND NC VDD RCP GND VDD GND VDD GND VDD RT LP RSCLK
GND VDD XI XO TCP GND VDD GND VDD GND OP3 SYMCLK TXEN
52 OP1 NC NC VDD SDI NC RDL RDH VDD NC OP2 TDH TDL 1
40 39
MX98704
13 14
27 26
SDO RDA0 RDA1 RDA2 RDA3 RDA4 TS TDA0 TDA1 TDA2 TDA3 TDA4 TCKIN
GND VDD XI XO TCP GND VDD GND VDD GND OP3 SYMCLK TXEN
3
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MX98704
4.0 PIN DESCRIPTIONS
MX Physicial Data Transceiver (PDTR) Function Pin PIN (PLCC) PIN (PQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 PIN NAME TYPE GND VDD GND Test VDD N/C GND OP1 N/C N/C VDD SDI N/C RDL RDH VDD NC OP2 TDH I I I O I O Parameter Option (GND is recommended) Transmit Data. These transmit output carrier differential NRZ data. They can be forced to logical 0 (TDH Low, TDL high) by asserting the TXEN input. Transmit Data. These transmit output carrier differential NRZ data. They can be forced to logical 0 (TDH Low, TDL high) by asserting the TXEN input. Ground. Power Supply. 5V 25MHz Transmit clock. These pins are 25MHz crystal connection for transmit clock. 25MHz Transmit colck. These pins are 25MHz crystal connection for transmit clock. Received Data. (Differential Line Receiver Inputs). These pins receive NRZI data. Received Data. (Differential Line Receiver Inputs). These pins receive NRZI data. Power Supply. 5V I I power Supply. 5V Signal Detect Input. This signal indicates that the received signal is above the detection threshold. I I Ground. Parameter Option (GND is recommended) I I I O I DESCRIPTION Ground. Power Supply. 5V Ground. Receiver Filter. Power Supply. 5V
20
13
TDL
O
21 22 23 24
14 15 16 17
GND VDD XTALI XTALO
I I I O
4
INDEX
MX98704
PIN (PLCC) PIN (PQFP) PIN NAME 25 26 27 28 29 30 31 32 33 18 19 20 21 22 23 24 25 26 Test GND VDD GND VDD GND OP3 SYMCLK TXEN TYPE O I I I I I O O I DESCRIPTION Transmit Filter. Ground. Power Supply. 5V Ground. Power Supply. 5V Ground. Parameter Option (GND is recommended) Local Symbol Clock. This pin supplies the frequency reference to the transmit logic. It is the buffered 25MHz oscillator output. Transmit Enable. When held LOW, the TDH output is forced LOW, and TDL output is forced HIGH so that the transmitter will output logical 0. This TTL-level signal has an internal pullup resistor. Transmit Clock In. This pin is a 25Mhz optional clock input. Transmit Data. These five inputs are 4B/5B encoded transmit data symbols, latched by the rising edge of SYMCLK. TDAT4 is the Most Significant Bit. Three-State. While this pin input is low, the interface output pins are forced into the high-impedance state. Pins controlled by this signal are PDAT4-0, SDO, BYTCLK, SYMCLK and RSCLK. This TTL-level signal has an internal pullup resistor. Receive Data. These 5-bit parallel data symbols from transceiver are clocked by the falling edge of RSCLK and carry the NRZ data symbols to the controller. RDAT4 is the Most Significant Bit. Signal Detect Output. SDO is the SDI input Asynchronized by RSCLK. It has the same logical sense as SDI. Recovered Symbol Clock. This is a 25MHz clock, which is derived from the receive clock synchronization PLL circuit. It is synchronous to the received serial data, and is the recovered bit clock divided-by-five. Loopback. (Active LOW) The function is used during system loopback test to bypass the transmission medium. This TTLlevel signal has an internal pullup resistor. Test Mode Enable. When asserted, the PDTR is in Test mode. For normal operation, TEST pin must be tied High. This TTLlevel signal has an internal pullup resistor. Power Supply. 5V Ground. Power Supply. 5V
34 35-39
27 28-32
TCLKIN TDAT4-0
I I
40
33
TSB
I
41-45
34-38
RDAT4-0
O
46 47
39 40
SDO RSCLK
O O
48
41
LPBKB
I
49
42
TEST
I
50 51 52
43 44 45
VDD GND VDD
I I I
5
INDEX
MX98704
5.0 FUNCTIONAL DESCRIPTION
Functional block diagram of the complete chip.
TDAT4-0
Input Register
Shifter
NRZ/ NRZI
Output Control
TDH, TDL
SYMCLK
TXEN
XTAL1, XTAL2 TCLKIN
25 Mhz Crystal Oscillator
Clock Multiplier (PLL)
NRZ/ NRZI RDAT4-0 Output Register Shifter Media Interface RDH, RDL
SDO RSCLK Divided by 5 Clock & Data Recovery (PLL) Clock Generator Control Logic MUX Normal Mode Test & Loopback Signal Detect SDI
TEST LPBKB
Data Transceiver Functions Block Diagram
5.1
NORMAL OPERATION MODE
The 5-bit data symbols to be transmitted are input from the PDTR chip on TDAT4-TDAT0.. The 5-bit symbol is latched into the PDT by the rising edge of SYMCLK, serialized and shifted to the output (TDAT4 bit is the first bit transmitted, and TDAT0 is the last bit transmitted). The TDH/TDL pair is connected to the serial link. To generate the serial link data rate, the PDT uses SYMCLK as the frequency reference. All of the internal logic of PDT runs on an internal clock that is PLL-multiplied from the external reference source. The PDT's internal PLL is referenced to the falling edge of SYMCLK only. The input clock frequency required to achieve 125 Mbaud on serial link is 25MHz at SYMCLK. The external TCLKIN or external Crystal reference clock (XTAL1, XTAL2) must meet I.E.E.E. frequency and stability requirements. The PDT serial output typically contains less than 0.4ns peak-to-peak jitters at 125 Mbaud. The latency from the SYMCLK to the serial output is typical 4 to 6 bits (8 ns/bit). The PDR accepts encoded NRZI serial data on the RDH/ RDL inputs. It latches the unframed symbol (5 bits) to the RDAT4-0 outputs on the falling edge of RSCLK. Five new bits are valid on each rising edge of RSCLK. RDAT4 is the first bit received and RDAT0 is the last bit received from the serial interface. The heart of PDR is its clock-recovery PLL, which extracts encoded clock information from the serial NRZ data stream and recovers the data. The PLL examines every data transition in the received serial stream and aligns its internal bit clock with these data transitions. In order to guarntee the correct operaion of PLL, the encoding scheme (4B/5B) must ensure adequate transition density of the encoded data stream.
6
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MX98704
The SDI input qualifies the data at RDH/ RDL. When SDI is LOW, the PDR uses SYMCLK as the PLL input reference. The LPBKB input selects the data source between RDH/ RDL and internal. When LPBKB is LOW, the SDI input is ignored.
5.2
TRANSMIT FUNCTIONS BLOCK
The transmitter consists of several blocks: 5.2.1 CLOCK MULTIPLIER
TCLKIN or Crystal Oscillator supplies the reference frequency which is multiplied by five using an on-chip PLL. The transmission rate and all serialization logic are controlled by the internally generated bit clock. 5.2.2 INPUT REGISTER
TDAT4-0 are clocked into the input Resister by the rising edge of SYMCLK. 5.2.3 SHIFT
Parallel data are loaded from the input Resistor into the Shifter at the internally generated symbol boundary, and serially shifted at the bit clock rate. 5.2.4 NRZ TO NRZI CONVERTER
The NRZ output of the Shifter is converted into NRZI data patterns for transmission. 5.2.5 OUTPUT CONTROL
The differential outputs carry the encoded serial NRZI bit stream. The TDH/ TDL pair can be forced to logical 0 (TDH LOW, TDL HIGH) by asserting TXEN input.
5.3
RECEIVER FUNCTIONS BLOCK
The receiver consists of several blocks: 5.3.1 CLOCK AND DATA RECOVERY PLL
The clock-recovery PLL separates the input data stream into clock and data patterns. The RSCLK is the recovered bit clock divided by five. This is a 25MHz clock. 5.3.2 MEDIA INTERFACE
The RDH/ RDL inputs are typically driven by differential PECL voltages, referenced to +5V. These inputs accept the encoded NRZI serial data.
7
INDEX
MX98704
5.3.3 SIGNAL DETECT (SD)
SDO is a level translation of SDI and indicates whether the receiver on SDI is receiving enough energy to produce a correct output. When SDO is not asserted low, RDAT4-RDAT0 are forced low. The system is in quite condition. SDO is an asynchronous signal that changes whenever the SDI change states. 5.3.4 NRZI TO NRZ CONVERTER
Serial data are retimed and associated jitter is removed. Retimed data are converted into NRZ format prior to the Shifter input. 5.3.5 SHIFT
The Shifter is serially loaded to parallel convert, using the recovered bit clock. 5.3.6 OUTPUT REGISTER
The Output Register is clocked by RSCLK falling edges. RSCLK is the recovered bit clock divided by five and is synchronous to the received serial data.
6.0 ABSOLUTE MAXIMUM RATINGS
Logic Power Referenced to GND Received Power Referenced to RGND Transmit Power Referenced to TGND ECL output Power Referenced to GND DC output current (High) ESD Storage Temperature -0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -0.5V to +0.7V -50mA 2000V -6.5C to +150C
7.0 ELECTRICAL CHARACTERISTICS
7.1 MAXIMUM RATINGS
RATING Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Junction Temperature SYMBOL Vcc Vin Ta Tstg Tj MIN -0.3 -0.3 0 -56 -40 MAX +7.0 Vcc 70 +150 +130 UNIT Vdc Vdc C C C
8
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MX98704
7.2 DC ELECTRICAL CHARACTERISTICS
CHARACTERISTIC Supply Voltage Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High ECL Output Voltage High ECL Output Voltage Low Power Supply Current Supply Voltage Purity SYMBOL Vcc Vil Vih Vol Voh Voh Vol Idd Vcc 50 MIN -0.3 -0.3 2.0 0.4 2.4 Vcc-1.1 Vcc-1.9 Vcc-0.8 Vcc-1.6 75 mVP-P MAX +7.0 0.8 VCC+0.3 UNIT Vdc Vdc Vdc Vdc Vdc Vdc Vdc ma
7.3
PARALLEL INTERFACE PARAMETERS
NUM 1 2 3 4 5 6 7 8 9 10 PARAMETER RSCLK Period RSCLK Time Low RSCLK Time Low Time to RDATA invalid Time to RDATA valid SYMCLK Period SYMCLK Time Low SYMCLK Time High TDATA Setup Time TDATA Hold Time MIN 33 20 14 8 20 33 20 14 12 0 MAX 50 20 26 20 32 50 26 20 40 28 UNIT ns ns ns ns ns ns ns ns ns ns
9
INDEX
MX98704
7.3.1 PARALLEL INTERFACE TIMING DIAGRAM
1 2 3
RSCLK
RDATA4-RDATA0
VALID
5 7
VALID
4 8
VALID
SYMCLK (TCLKIN)
6
TDATA4-TDATA0
9 10
7.4
TCLKIN TIMING PARAMETERS
NUM 11 12 13 PARAMETER TCLKIN Period TCLKIN Time Low TCLKIN Time High TCLKIN TIMING MIN 33 8 8 MAX 50 UNIT ns ns ns
7.4.1
11 13 12 20V
0.8V
10
INDEX
MX98704
7.5 ECL TIMING PARAMETERS
NUM 14 15 PARAMETER ECL Rise Time ECL Fall Time MIN 0.9 0.9 MAX 3.0 3.0 UNIT ns ns
7.5.1
ECL TIMING
14 15
4.0V
3.3V
8.0 ORDER INFORMATION
PARTS NO. MX98704QC MX98704EC PACKAGE 52-PIN PLCC 52-PIN PQFP
11
INDEX
MX98704
9.0 PACKAGE INFORMATION
9.1 52-PIN PLCC
D D1
4 5
1
25 24
ITEM D D1 E E1 D2 A A1 H I K
MILLIMETERS 20.066 19.126 20.066 19.126 18.034 4.572 2.667 .762 1.27 0.457
INCHES .790 .753 .790 .753 .710 .180 .105 .03 .05 .018
E1
E
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
11 12 17
18
A
A1
H I K
D2
12
INDEX
MX98704
9.2 52-PIN PQFP
He E
ITEM A1 A2 b D E e Hd He L L1
MILLIMETERS 0.25 2.05 0.3 10 10 0.65 13.2 13.2 0.8 1.6
INCHES 0.01 0.81 0.012 0.394 0.394 0.026 0.52 0.52 0.031 0.063
52 1 14 13 A2 D Hd 40 39 27 26
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
b
e L1
A2 A1 L
13
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MX98704
MACRONIX INTERNATIONAL CO., LTD
HEADQUARTERS :
TEL : +886-3-578-8888 FAX : +886-3-578-8887
EUROPE OFFICE :
TEL : +32-2-456-8020 FAX : +32-2-456-8021
JAPAN OFFICE :
TEL : +81-44-246-9100 FAX : +81-44-246-9105
SINGAPORE OFFICE :
TEL : +65-747-2309 FAX : +65-748-4090
TAIPEI OFFICE :
TEL : +886-2-2509-3300 FAX : +886-2-2509-2200
MACRONIX AMERICA INC.
TEL : +1-408-453-8088 FAX : +1-408-453-8488
CHICAGO OFFICE :
TEL : +1-847-963-1900 FAX : +1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
14
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MX98704
D D1
ITEM D D1 E E1 D2 A H I K
MILLIMETERS 12.535 12.015 12.535 12.015 10.7 4.38 .510 1.27 0.455
INCHES .492 .452 .492 .452 .420 .172 .020 .050 .018
11 5
4
1
25 24
E1 E
18
12
17
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
A A1
H I K
D2
15

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